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Electronic Circuit Board

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In the world of Universal Verification Methodology (UVM), the ability to create AXI protocol simulations plays a crucial role in ensuring our designs work flawlessly. Previously, we discussed the importance of creating AXI sequences and transaction items, which lay the groundwork for simulating read/write operations effectively. Today, we will go one step further: we'll describe how to build a complete UVM environment, integrating master/slave agents with an RTL DUT (Design Under Test). By the end, you’ll have a clear understanding of how individual UVM components interact to verify AXI-compliant designs.



To start, let’s break down the UVM architecture into digestible pieces. Our primary components are the **driver (drv)**, **sequencer (seqr)**, **monitor (mon)**, and **agent (combines driver, sequencer, and monitor)**. These components handle communication between the AXI protocol’s **master** (the stimulus generator) and its **slave** (the recipient model implemented as a DUT).

At the center of all activity lies the **txn** object, which models AXI read/write operations (like `read(address)`), managed by the **sequencer (seqr)** and executed by the **driver (drv)**. To interface the DUT with UVM and create repetitive AXI transactions (read/write), we’ll implement a virtual interface called **axi_if**. Additionally, the **monitor (mon)** will observe the transactions for both master and slave sides, ensuring we can later track and verify correctness.



To better understand this setup, let’s consider a real-life scenario. Imagine two friends, Alice and Bob, where Alice writes a message on a chalkboard (write operation), and Bob reads the message (read operation). The chalkboard represents the DUT (our shared communication medium), while Alice and Bob must follow agreed-upon rules: Alice writes in one section (master), and Bob reads from another section (slave). If Alice writes incorrect data, Bob will get the wrong message.

Our UVM environment replicates this scenario. The chalkboard (DUT) connects Alice (master agent) and Bob (slave agent) using a standard interface (**axi_if**). Meanwhile, our **monitor (mon)** acts as a teacher, watching Alice and Bob to ensure they don’t break writing/reading rules.

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