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Below is Article 13 (Part 2), continuing cleanly from Part 1.

This article is written so that most inheritance & polymorphism interview questions become answerable after reading, not just recognizable.
Same Alice–Bob mental model, depth over breadth, no overload.

Article 13 (Part 2): Inheritance & Polymorphism in SystemVerilog — Why virtual Exists

1. Why This Topic Exists (Real Problem First)

In Part 1, Alice learned to create objects using classes.

Now she faces a new problem:

I have many similar objects, but with small differences.
I don’t want to rewrite the same code again and again.

This is where inheritance and polymorphism exist — not for syntax, but for reuse + flexibility.

2. What Are Inheritance and Polymorphism? (Interview-Safe Definition)

Inheritance allows one class to reuse and extend another class, while polymorphism allows a base-class handle to refer to different derived-class objects and call the correct behavior at runtime.

Key words:

  • reuse

  • extend

  • base handle

  • runtime decision

If these are clear, you’re already ahead.

3. Alice–Bob Mental Model (Lock This In)

  • Alice defines a general idea → base class

  • Bob creates specific versions → derived classes

  • Bob talks only to the general interface

  • Actual behavior depends on the real object underneath

This separation is the core idea.

4. Inheritance — “Is-a” Relationship

Mental Picture

Alice defines:

“A packet is something that has address and data.”

Later she says:

“A read packet is also a packet.”
“A write packet is also a packet.”

That “also” is inheritance.

Basic Inheritance Example

class packet;

  int addr;

 

  function void display();

    $display("Base packet, addr=%0d", addr);

  endfunction

endclass

 

class read_packet extends packet;

  function void display();

    $display("Read packet, addr=%0d", addr);

  endfunction

endclass

 

Here:

  • read_packet inherits addr

  • It extends behavior by redefining display()

5. The Trap: Inheritance Alone Is NOT Enough

Now Bob writes this:

module inheritance_trap;

  initial begin

    packet p;

    p = new read_packet();

    p.addr = 10;

    p.display();

  end

endmodule

 

Interview Question:

What prints?

Actual Output:

Base packet, addr=10

 

❗ This surprises beginners.

6. Why Did This Happen? (Critical Understanding)

Because:

  • The handle type is packet

  • The method call is resolved at compile time

  • SystemVerilog assumes non-virtual methods

So even though:

  • Object is read_packet

  • Handle is packet

The base version is called.

👉 Inheritance without polymorphism is incomplete.

7. virtual — Why It Exists (This Is the Core)

To tell System Verilog:

“Do NOT decide behavior at compile time.
Decide at runtime based on actual object.”

That instruction is the keyword virtual.

8. Correct Polymorphic Code (Very Important)

Base Class (Declare Method as virtual)

class packet;

  int addr;

 

  virtual function void display();

    $display("Base packet, addr=%0d", addr);

  endfunction

endclass

Derived Class (Override)

class read_packet extends packet;

  function void display();

    $display("Read packet, addr=%0d", addr);

  endfunction

endclass

Runtime Behavior (Now Correct)

module polymorphism_example;

  initial begin

    packet p;

    p = new read_packet();

    p.addr = 10;

    p.display();

  end

endmodule

 

Output:

Read packet, addr=10

 

👉 This is true polymorphism.

9. Alice–Bob Explanation (Why This Matters)

  • Alice writes common code using base handles

  • Bob plugs in different derived objects

  • Alice does NOT change her code

  • Behavior adapts automatically

This is why UVM and verification rely heavily on polymorphism.

10. Why Interviewers LOVE virtual

Because many candidates:

  • Know inheritance syntax

  • Do NOT understand virtual

  • Fail to explain runtime dispatch

This topic separates:

  • Syntax learners ❌

  • Verification engineers ✅

11. Common Interview Traps (Now You Can Handle Them)

Trap 1

“Inheritance automatically gives polymorphism.”

❌ False
✔ Only with virtual

Trap 2

“Object type decides method call.”

❌ False
✔ Handle type + virtual decide behavior

Trap 3

“Why not make everything virtual?”

✔ Virtual has runtime cost
✔ Use it only where polymorphism is needed

12. Class vs Class (Base vs Derived) — One Table

Aspect               | Base Class                 | Derived Class
Purpose              Common behavior     Specialized behavior
Handles              Often used                   Rarely exposed
Methods             Usually virtual              Usually override
Interview focus   Very high                     High

13. Interview Questions (Now Fully Answerable)

Easy

  1. What does extends mean?

  2. What is inheritance?

Medium

  1. Why did base method get called instead of derived?

  2. What does virtual change?

Hard

  1. Why does System Verilog require virtual explicitly?

  2. Why is polymorphism critical in verification?

  3. What breaks if virtual is forgotten?

If you can answer these, you’re strong.

14. One Sentence to Remember (Interview Gold)

Inheritance reuses code, virtual enables runtime behavior selection.

Repeat this — it sticks.

15. What’s Next

Now Alice can:

  • Create objects

  • Reuse code

  • Change behavior at runtime

Next, she wants to:

Generate varied stimulus automatically.

👉 Next Article:
Randomization Basics — rand, randc, and Why They Exist

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