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Great — this topic absolutely deserves depth.
Randomization is one of the highest ROI interview areas in SystemVerilog verification, and shallow coverage causes people to fail follow-ups.

Below is Article 14, written to ensure that after reading it, ~70–80% of randomization interview questions are answerable.

  • Many situations

  • Many examples

  • Strong Alice–Bob reasoning

  • Focus on why, not just syntax

  • Still readable and structured (but not bloated)

Article 14: Randomization in SystemVerilog — rand, randc, and How Verification Really Works

1. Why Randomization Exists (Real Verification Problem)

Up to now, Alice has been writing fixed tests:

  • Apply value A

  • Check output

  • Apply value B

  • Check output

This works — but only for known cases.

Now Alice faces a real verification challenge:

How do I test scenarios I didn’t think of?
How do I explore corner cases automatically?

Hard-coding values does not scale.

This is exactly why randomization exists.

2. What Is Randomization in System Verilog? (Interview-Safe Definition)

Randomization in System Verilog allows variables to take randomized values automatically, enabling broad functional coverage and discovery of corner-case bugs without writing exhaustive tests.

Key idea:

We randomize inputs, not behavior.

3. Alice–Bob Mental Model (Lock This In)

  • Alice = stimulus generator

  • Bob = checker

  • Alice does not choose exact values

  • She chooses rules

  • SystemVerilog fills in values

Alice says:

“Give me many legal scenarios — I’ll verify behavior.”

4. rand — Basic Random Variable (Foundation)

What rand Means

rand int a;

 

This means:

  • a can be randomized

  • Value is chosen when randomize() is called

  • Each randomization is independent

Basic Runnable Example

class basic_rand;

  rand int a;

endclass

 

module rand_example;

  initial begin

    basic_rand obj = new();

 

    repeat (3) begin

      obj.randomize();

      $display("a = %0d", obj.a);

    end

  end

endmodule

 

What to Observe

  • Each call produces a new value

  • No guarantee of uniqueness

  • Values may repeat

5. Interview Question (Easy)

Q: When does randomization actually happen?
✔ Answer: When randomize() is called

This question is asked very often.

6. randc — Cyclic Randomization (Very Important)

Why randc Exists

Alice now says:

“I don’t want repeats until all values are used.”

This is common in verification:

  • IDs

  • Sequences

  • Small address ranges

That is what randc solves.

randc Example

class cyclic_rand;

  randc bit [2:0] id; // values 0–7

endclass

 

module randc_example;

  initial begin

    cyclic_rand obj = new();

 

    repeat (8) begin

      obj.randomize();

      $display("id = %0d", obj.id);

    end

  end

endmodule

 

Key Property

  • No repetition until cycle completes

  • After exhaustion, cycle restarts

7. Interview Question (Medium)

Q: Difference between rand and randc?

✔ rand → values may repeat
✔ randc → values cycle without repetition

If you say this clearly, you pass.

8. Randomization Happens Only in Classes (Critical Rule)

This Will NOT Work

rand int a;  // ❌ illegal outside class

 

Why?

Because:

  • Randomization is object-oriented

  • It relies on methods and state

  • Classes provide that structure

Interview Trap Question

Q: Can you randomize a variable declared in a module?

✔ Correct answer: No, randomization is class-based

9. Alice Uses Randomization Correctly (Full Flow)

Situation

Alice wants to:

  • Generate many transactions

  • Each with random address and data

Runnable Example

class transaction;

  rand bit [7:0] addr;

  rand bit [7:0] data;

 

  function void display();

    $display("addr=%0h data=%0h", addr, data);

  endfunction

endclass

 

module rand_transaction_example;

  initial begin

    transaction t = new();

 

    repeat (3) begin

      t.randomize();

      t.display();

    end

  end

endmodule

 

Here:

  • Alice defines rules

  • SystemVerilog generates values

  • Bob checks behavior

10. Common Beginner Misunderstanding (Very Important)

Misunderstanding:

“Randomization picks values automatically.”

Reality:

Randomization happens ONLY when randomize() is called.

No call → no new values.

11. Controlling Randomization (Preview, Interview-Relevant)

Even before constraints, Alice can do this:

t.randomize() with { addr < 16; };

 

This is called inline constraint.

Interviewers love asking:

“How do you control randomness?”

This is the first correct answer.

(Constraints will be covered in the next article in depth.)

12. Debug Visibility — Why Randomization Is Powerful

Randomization:

  • Exposes corner cases

  • Finds bugs you didn’t think of

  • Forces design robustness

But:

  • Poorly controlled randomization causes chaos

  • That’s why constraints matter (next article)

13. Common Interview Questions — Now Answerable

After this article, you should be able to answer:

  • What is rand?

  • What is randc?

  • Difference between rand and randc

  • When does randomization occur?

  • Why is randomization class-based?

  • Can randomization happen without randomize()?

These cover most basic interview filters.

14. One Sentence to Remember (Interview Gold)

Randomization generates values when randomize() is called; randc avoids repetition.

If this is clear, you’re strong.

15. What’s Next (Very Important)

Now Alice can randomize —
but randomness without rules is dangerous.

Next, she asks:

How do I restrict random values to legal scenarios?

👉 Next Article:
Constraints in SystemVerilog — Simple & Inline Constraints

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