Introduction

If there is one SystemVerilog topic that interviewers use to separate:

• people who write code

• from people who understand simulation

…it is blocking vs non-blocking assignments.

Almost every verification interview includes:

• = vs <=

• race conditions

• “why non-blocking for flops?”

This topic exists because simulation executes in time and order, not magically like hardware.

 

What Is the Difference Between Blocking and Non-Blocking Assignments?

In SystemVerilog, blocking assignments (=) execute immediately and block the next statement, while non-blocking assignments (<=) schedule updates to occur later, typically at the end of the current time step.

Short version:

• = → do it now

• <= → do it after everyone is done

That timing difference is everything.

 

Alice & Bob Mental Model (Lock This In)

• Alice writes procedural code

• Bob is the simulator

• Bob executes code line by line

• Bob also has a scheduler for delayed updates
   

Alice must tell Bob:

• “Update now”

• or “Update later"

That choice is = vs <=.

 

Blocking Assignment (=) — “Do It Now”

How Bob Executes Blocking Assignments

Bob sees:

a = b;

c = a;

He executes:

1. assign a

2. immediately use new a for c

Nothing is delayed.

 

Runnable Example — Blocking Behavior

module blocking_example;

  int a, b, c;

 

  initial begin

    b = 10;

    a = b;

    c = a;

    $display("a=%0d c=%0d", a, c);

  end

endmodule

 

Output:

a=10 c=10

 

This is intuitive and predictable.

 

Where Blocking Is Correct

Blocking assignments are correct and recommended in:

• combinational logic

• always_comb

• testbench procedural code

• temporary variables
   

Interview-safe statement:

Blocking assignments model step-by-step execution.

 

Non-Blocking Assignment (<=) — “Do It Later”

What “Later” Actually Means

When Bob sees:

a <= b;

 

He does not update a immediately.

Instead:

• he schedules the update

• all scheduled updates happen together

• after the current time slot
   

This models hardware registers.

 

Runnable Example — Non-Blocking Timing

module nonblocking_example;

  int a, b;

 

  initial begin

    b = 5;

    a <= b;

    $display("Inside block: a=%0d", a);

    #0;

    $display("After update: a=%0d", a);

  end

endmodule

 

Key idea:

• first display shows old a

• update happens later

This surprises beginners — interviewers love this.

 

Alice’s Big Mistake — Blocking in Sequential Logic

The Classic Bug (Very Common)

always_ff @(posedge clk) begin

  q = d;

end

 

What Alice thinks:

This is a flip-flop

What Bob does:

Immediate update → simulation mismatch risk

This can cause:

• race conditions
   

• incorrect simulation ordering
   

• bugs that disappear in synthesis
   

 

Correct Sequential Modeling (Unforgettable Rule)

always_ff @(posedge clk) begin

  q <= d;

end

 

Now Bob:

• samples inputs

• updates all registers together

• matches real hardware
   

 

The Golden Rule (Interview Gold)

Blocking for combinational logic, non-blocking for sequential logic.

If you say this confidently, most interviewers stop pushing.

 

Race Condition Example (Why This Matters)

❌ Wrong Code (Blocking in Sequential)

always_ff @(posedge clk) begin

  a = b;

  c = a;

end

 

Here:

• c gets new a
   

• ordering matters
   

• race risk increases
   

 

✅ Correct Code (Non-Blocking)

always_ff @(posedge clk) begin

  a <= b;

  c <= a;

end

 

Now:

• both updates happen together
   

• c gets old a
   

• matches hardware pipeline behavior
   

 

Why Interviewers Care So Much

Because this topic proves whether you understand:

• simulation scheduling

• delta cycles

• hardware vs software thinking

Anyone can memorize syntax.
Only understanding explains why.

 

Common Interview Questions (Now Answerable)

Why non-blocking for flops?
→ To model simultaneous register updates.

Can blocking cause race conditions?
→ Yes, especially in sequential logic.

Can non-blocking be used in combinational logic?
→ Technically yes, but strongly discouraged.

What happens if you mix = and <=?
→ Unpredictable ordering and bugs.

 

Common Beginner Mistakes (Reality-Based)

• Using = everywhere out of habit
   

• Mixing = and <= in the same block
   

• Thinking non-blocking is “slower”
   

• Not understanding when updates occur
   

 

One Sentence to Remember (Interview Friendly)

Blocking assignments execute immediately, non-blocking assignments schedule updates to occur together later.

This sentence alone can become a featured snippet.

 

What’s Next

Now Alice understands:

• where logic lives (always_*)
   

• how values update (= vs <=)
   

The next natural question is:

“How do I put reusable behavior into procedures?”

👉 Next Article:
Tasks vs Functions — Timing, Side Effects, and Interview Traps