Demystifying AXI: A Simple AXI Slave for Basic Read and Write Transactions

In the previous discussion, we introduced the Advanced eXtensible Interface (AXI) protocol, detailing its various transaction types—such as Read Address (AR), Read Data (R), Write Address (AW), Write Data (W), and Write Response (B). These transaction types establish communication between AXI master and slave devices, enabling efficient data transfers. Building on this foundation, this article will provide a Verilog RTL implementation of a simple AXI slave that supports basic read and write operations, focusing on signal-level behaviors. By the end, you'll have a clear understanding of how an AXI slave operates within a system.

To delve into this topic, let us begin with the basic read and write operations that form the backbone of AXI transactions. The AXI slave operates based on signals received from the AXI master, like `addr`, `data`, `ready`, and `valid`. During a write operation, the master sends a write address (AW) and write data (W) to the slave. Once received and validated, the slave generates a response (B) indicating whether the operation was successful. On the other hand, read operations involve the master sending a read address (AR) to the slave, which responds with the requested data (R).

To simplify the understanding of this concept, consider two friends, Alice (the AXI master) and Bob (the AXI slave). Alice asks Bob for a specific book by providing its index in a library. Bob fetches the book and gives it to Alice. Alternatively, Alice asks Bob to add a new book to the shelf at a specific location and waits until Bob confirms it's been stored properly. In this analogy, Alice's requests are similar to AR/AW signals, Bob fetching or storing the book corresponds to R/W data responses, and Bob's confirmation represents the B response.

In practical terms, this library example mirrors the read/write interactions between an AXI master (Alice) and an AXI slave (Bob). The slave needs to use its resources to store or retrieve the requested information, ensuring the operations comply with the AXI protocol's handshake mechanism through `valid` and `ready` signals. To bring this to life in hardware, let us implement a basic RTL model of an AXI slave using Verilog.

Here is the Verilog RTL implementation for a simple AXI slave. The slave reads or writes from an internal memory array as directed by transactions from the master.

```verilog
// Simple AXI Slave Verilog Implementation
module simple_axi_slave #(
parameter ADDR_WIDTH = 8, // Address width
parameter DATA_WIDTH = 32 // Data width
)(
input wire aclk, // AXI clock
input wire aresetn, // Active-low reset

// AXI Write Address Channel
input wire [ADDR_WIDTH-1:0] awaddr, // Write address
input wire awvalid, // Write address valid
output reg awready, // Write address ready

// AXI Write Data Channel
input wire [DATA_WIDTH-1:0] wdata, // Write data
input wire wvalid, // Write data valid
output reg wready, // Write data ready

// AXI Write Response Channel
output reg [1:0] bresp, // Write response
output reg bvalid, // Write response valid
input wire bready, // Write response ready

// AXI Read Address Channel
input wire [ADDR_WIDTH-1:0] araddr, // Read address
input wire arvalid, // Read address valid
output reg arready, // Read address ready

// AXI Read Data Channel
output reg [DATA_WIDTH-1:0] rdata, // Read data
output reg rvalid, // Read data valid
input wire rready // Read data ready
);

// Memory to hold data
reg [DATA_WIDTH-1:0] mem [(2**ADDR_WIDTH)-1:0];

// Reset process
always @(posedge aclk or negedge aresetn) begin
if (!aresetn) begin
awready <= 0;
wready <= 0;
bvalid <= 0;
arready <= 0;
rvalid <= 0;
end else begin
// ---- Write Address Handshake ----
if (awvalid && !awready) begin
awready <= 1; // Slave is ready to accept the write address
end else begin
awready <= 0;
end

// ---- Write Data Handshake ----
if (wvalid && !wready) begin
wready <= 1; // Slave is ready to accept the write data
mem[awaddr] <= wdata; // Writing data to memory
end else begin
wready <= 0;
end

// ---- Write Response Generation ----
if (wready && !bvalid) begin
bvalid <= 1; // Response valid
bresp <= 2'b00; // OKAY response
end else if (bready) begin
bvalid <= 0;
end

// ---- Read Address Handshake ----
if (arvalid && !arready) begin
arready <= 1; // Slave is ready to accept the read address
end else begin
arready <= 0;
end

// ---- Read Data Generation ----
if (arready && arvalid && !rvalid) begin
rvalid <= 1; // Data valid
rdata <= mem[araddr]; // Read data from memory
end else if (rready) begin
rvalid <= 0;
end
end
end
endmodule
```