Coverage in SystemVerilog (Part 1) — Why Random Tests Alone Are Not Enough (With Code)

𝐈𝐧𝐭𝐫𝐨𝐝𝐮𝐜𝐭𝐢𝐨𝐧

Alice has done a lot already:

• random stimulus

• constraints

• assertions

Her simulation runs clean. No errors.

Bob now asks the uncomfortable question:

  “How do you know you actually tested anything meaningful?”

Silence usually follows.

This is why coverage exists — to measure what really happened, not what could have happened.

𝐖𝐡𝐚𝐭 𝐈𝐬 𝐂𝐨𝐯𝐞𝐫𝐚𝐠𝐞 𝐢𝐧 𝐒𝐲𝐬𝐭𝐞𝐦𝐕𝐞𝐫𝐢𝐥𝐨𝐠?

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𝐂𝐨𝐯𝐞𝐫𝐚𝐠𝐞 𝐢𝐧 𝐒𝐲𝐬𝐭𝐞𝐦𝐕𝐞𝐫𝐢𝐥𝐨𝐠 𝐦𝐞𝐚𝐬𝐮𝐫𝐞𝐬 𝐰𝐡𝐢𝐜𝐡 𝐯𝐚𝐥𝐮𝐞𝐬, 𝐬𝐜𝐞𝐧𝐚𝐫𝐢𝐨𝐬, 𝐨𝐫 𝐛𝐞𝐡𝐚𝐯𝐢𝐨𝐫𝐬 𝐡𝐚𝐯𝐞 𝐨𝐜𝐜𝐮𝐫𝐫𝐞𝐝 𝐝𝐮𝐫𝐢𝐧𝐠 𝐬𝐢𝐦𝐮𝐥𝐚𝐭𝐢𝐨𝐧, 𝐡𝐞𝐥𝐩𝐢𝐧𝐠 𝐪𝐮𝐚𝐧𝐭𝐢𝐟𝐲 𝐯𝐞𝐫𝐢𝐟𝐢𝐜𝐚𝐭𝐢𝐨𝐧 𝐜𝐨𝐦𝐩𝐥𝐞𝐭𝐞𝐧𝐞𝐬𝐬.

Coverage does not check correctness.

Coverage checks exploration.

𝐀𝐥𝐢𝐜𝐞 & 𝐁𝐨𝐛 𝐌𝐞𝐧𝐭𝐚𝐥 𝐌𝐨𝐝𝐞𝐥

• Alice generates tests

• Bob observes execution

• Bob keeps counters:

“This happened”

“This never happened”

Coverage is Bob’s notebook, not Alice’s logic.

𝐅𝐢𝐫𝐬𝐭 𝐓𝐚𝐬𝐭𝐞: 𝐅𝐮𝐧𝐜𝐭𝐢𝐨𝐧𝐚𝐥 𝐂𝐨𝐯𝐞𝐫𝐚𝐠𝐞 𝐰𝐢𝐭𝐡 𝐑𝐞𝐚𝐥 𝐂𝐨𝐝𝐞

Let’s start simple and concrete.

Alice wants to know:

• Did addr ever take low values?

• Did it ever take high values?

She doesn’t care how it was generated — only if it happened.

𝐁𝐚𝐬𝐢𝐜 𝐂𝐨𝐯𝐞𝐫𝐠𝐫𝐨𝐮𝐩 𝐄𝐱𝐚𝐦𝐩𝐥𝐞 (𝐑𝐮𝐧𝐧𝐚𝐛𝐥𝐞)

module basic_coverage;

  int addr;

  covergroup addr_cg;

    coverpoint addr {

      bins low  = {[0:3]};

      bins mid  = {[4:7]};

      bins high = {[8:15]};

    }

  endgroup

  addr_cg cg = new();

  initial begin

    repeat (10) begin

      addr = $urandom_range(0,15);

      cg.sample();

      $display("addr = %0d", addr);

    end

  end

endmodule

𝐖𝐡𝐚𝐭 𝐈𝐬 𝐇𝐚𝐩𝐩𝐞𝐧𝐢𝐧𝐠 𝐇𝐞𝐫𝐞 (𝐕𝐞𝐫𝐲 𝐈𝐦𝐩𝐨𝐫𝐭𝐚𝐧𝐭)

• covergroup defines what to observe

• coverpoint defines which signal

• bins define interesting value ranges

• sample() records the current value

Alice does not force values.

She only measures what occurs.

𝐖𝐡𝐲 𝐓𝐡𝐢𝐬 𝐈𝐬 𝐏𝐨𝐰𝐞𝐫𝐟𝐮𝐥 (𝐈𝐧𝐭𝐞𝐫𝐯𝐢𝐞𝐰 𝐈𝐧𝐬𝐢𝐠𝐡𝐭)

Even if:

• addr never becomes 15

• simulation passes

Coverage will clearly show:

“high bin was never hit”

This tells Alice:

• testbench is incomplete

• constraints or stimulus must improve

𝐂𝐨𝐯𝐞𝐫𝐚𝐠𝐞 𝐯𝐬 𝐀𝐬𝐬𝐞𝐫𝐭𝐢𝐨𝐧𝐬 (𝐂𝐥𝐞𝐚𝐫 𝐃𝐢𝐟𝐟𝐞𝐫𝐞𝐧𝐜𝐞)

Let’s compare with an assertion.

assert (addr < 16)

  else $error("Invalid addr");

• Assertion checks correctness

• Coverage checks occurrence

Interview-safe sentence:

Assertions catch bugs; coverage reveals blind spots.

𝐂𝐨𝐝𝐞 𝐂𝐨𝐯𝐞𝐫𝐚𝐠𝐞 𝐯𝐬 𝐅𝐮𝐧𝐜𝐭𝐢𝐨𝐧𝐚𝐥 𝐂𝐨𝐯𝐞𝐫𝐚𝐠𝐞 (𝐖𝐢𝐭𝐡 𝐂𝐨𝐧𝐭𝐞𝐱𝐭)

Tools automatically collect code coverage:

• line coverage

• branch coverage

• toggle coverage

Alice does not write code for that.

Functional coverage is:

• written by Alice

• based on design intent

• scenario-driven

This is why functional coverage matters more in interviews.

𝐀𝐥𝐢𝐜𝐞 𝐌𝐚𝐤𝐞𝐬 𝐈𝐭 𝐌𝐨𝐫𝐞 𝐑𝐞𝐚𝐥𝐢𝐬𝐭𝐢𝐜

Now Alice wants to see:

• read vs write operations

• not just raw values

𝐑𝐮𝐧𝐧𝐚𝐛𝐥𝐞 𝐄𝐱𝐚𝐦𝐩𝐥𝐞 — 𝐌𝐮𝐥𝐭𝐢𝐩𝐥𝐞 𝐂𝐨𝐯𝐞𝐫𝐩𝐨𝐢𝐧𝐭𝐬

module op_coverage;

  bit write;

  int addr;

  covergroup op_cg;

    coverpoint write {

      bins read  = {0};

      bins write = {1};

    }

    coverpoint addr {

      bins low  = {[0:3]};

      bins high = {[12:15]};

    }

  endgroup

  op_cg cg = new();

  initial begin

    repeat (20) begin

      write = $urandom_range(0,1);

      addr  = $urandom_range(0,15);

      cg.sample();

      $display("write=%0d addr=%0d", write, addr);

    end

  end

endmodule

𝐖𝐡𝐚𝐭 𝐀𝐥𝐢𝐜𝐞 𝐋𝐞𝐚𝐫𝐧𝐬 𝐟𝐫𝐨𝐦 𝐓𝐡𝐢𝐬

After simulation:

• Did both read and write occur?

• Were both low and high addresses exercised?

No guessing.

Coverage data answers directly.

𝐂𝐨𝐦𝐦𝐨𝐧 𝐁𝐞𝐠𝐢𝐧𝐧𝐞𝐫 𝐌𝐢𝐬𝐭𝐚𝐤𝐞𝐬 (𝐖𝐢𝐭𝐡 𝐂𝐨𝐝𝐞 𝐂𝐨𝐧𝐭𝐞𝐱𝐭)

• Forgetting to call sample()

• Assuming coverage samples automatically

• Writing coverage without knowing intent

• Sampling at the wrong time

Interviewers often ask:

“When does coverage get sampled?”

Correct answer:

When sample() is called (unless clocked).

𝐎𝐧𝐞 𝐕𝐞𝐫𝐲 𝐈𝐦𝐩𝐨𝐫𝐭𝐚𝐧𝐭 𝐈𝐧𝐭𝐞𝐫𝐯𝐢𝐞𝐰 𝐏𝐨𝐢𝐧𝐭

Coverage does not improve tests automatically.

Alice must:

1. look at coverage reports

2. identify holes

3. improve stimulus or constraints

Coverage is feedback, not magic.

𝐈𝐧𝐭𝐞𝐫𝐯𝐢𝐞𝐰 𝐐𝐮𝐞𝐬𝐭𝐢𝐨𝐧𝐬 𝐘𝐨𝐮 𝐂𝐚𝐧 𝐍𝐨𝐰 𝐀𝐧𝐬𝐰𝐞𝐫

• What is functional coverage?

• What are covergroups and coverpoints?

• What are bins?

• How is coverage different from assertions?

• Does coverage affect simulation behavior?

All answerable from this article.

𝐎𝐧𝐞 𝐒𝐞𝐧𝐭𝐞𝐧𝐜𝐞 𝐭𝐨 𝐑𝐞𝐦𝐞𝐦𝐛𝐞𝐫 (𝐒𝐧𝐢𝐩𝐩𝐞𝐭 + 𝐈𝐧𝐭𝐞𝐫𝐯𝐢𝐞𝐰 𝐅𝐫𝐢𝐞𝐧𝐝𝐥𝐲)

Functional coverage measures which scenarios occurred during simulation, independent of correctness.

𝐖𝐡𝐚𝐭’𝐬 𝐍𝐞𝐱𝐭

👉 𝐍𝐞𝐱𝐭 𝐀𝐫𝐭𝐢𝐜𝐥𝐞:

Coverage in SystemVerilog (Part 2) — Cross Coverage, Bins, and Interview Traps