Coverage in SystemVerilog (Part 2) — Cross Coverage, Bins, and Real Scenarios (Code-First)

Introduction

In Part 1, Alice learned how to observe values using covergroups and bins.
Now she wants to answer harder questions:

Did combinations ever occur?
Did some values occur too often or never?
How do I exclude illegal or meaningless cases?

This is where cross coverage, ignore bins, and illegal bins become essential.

Cross Coverage — Did Two Things Happen Together?

Alice already tracks:

operation type (read / write)
address range

But Bob asks:

“Did writes ever happen at high addresses?”

That’s not a single signal it’s a combination.

Runnable Example — Basic Cross Coverage

module cross_coverage_basic;

bit write;

int addr;

covergroup cg;

coverpoint write {

bins read = {0};

bins write = {1};

}

coverpoint addr {

bins low = {[0:3]};

bins high = {[12:15]};

}

cross write, addr;

endgroup

cg cov = new();

initial begin

repeat (20) begin

write = $urandom_range(0,1);

addr = $urandom_range(0,15);

cov.sample();

$display("write=%0d addr=%0d", write, addr);

end

endmodule

What This Gives You

Coverage now records:

read + low
read + high
write + low
write + high

Alice can immediately see which combinations never occurred.

Why Cross Coverage Matters

Without cross coverage:

each signal may look “well tested”
critical combinations may be missing

Cross coverage prevents false confidence.

Ignore Bins — “I Don’t Care About These”

Alice realizes:

some combinations are meaningless
some scenarios are out of scope

She should not waste coverage effort on them.

Runnable Example — Ignore Bins

module ignore_bins_example;

bit write;

int addr;

covergroup cg;

coverpoint write {

bins read = {0};

bins write = {1};

}

coverpoint addr {

bins low = {[0:3]};

bins high = {[12:15]};

}

cross write, addr {

ignore_bins read_high =

binsof(write.read) && binsof(addr.high);

}

endgroup

cg cov = new();

initial begin

repeat (20) begin

write = $urandom_range(0,1);

addr = $urandom_range(0,15);

cov.sample();

end

endmodule

Meaning

Alice explicitly says:
- “Read at high address is irrelevant”
Coverage will not expect this combination

This keeps coverage meaningful, not inflated.

Illegal Bins — “This Must Never Happen”

Now Alice wants something stronger.

Some cases are not just irrelevant they are design bugs.

Runnable Example — Illegal Bins

module illegal_bins_example;

bit write;

int addr;

covergroup cg;

coverpoint write;

coverpoint addr {

bins valid = {[0:15]};

illegal_bins invalid = {[16:31]};

}

endgroup

cg cov = new();

initial begin

repeat (10) begin

write = $urandom_range(0,1);

addr = $urandom_range(0,20);

cov.sample();

$display("addr=%0d", addr);

end

endmodule

What Happens

If addr > 15, the illegal bin is hit
Simulator reports a coverage violation
Alice immediately knows something is wrong

This is coverage acting like a checker.

Automatic vs User-Defined Bins

By default, SystemVerilog can auto-create bins.

Alice usually prefers explicit bins for clarity.

Runnable Example — Automatic Bins

module auto_bins_example;

int data;

covergroup cg;

coverpoint data;

endgroup

cg cov = new();

initial begin

repeat (10) begin

data = $urandom_range(0,7);

cov.sample();

end

endmodule

This creates:

one bin per value (tool-dependent)

Good for:

quick exploration

Bad for:

intent-driven verification

Clocked Coverage — Sampling at the Right Time

So far, Alice sampled manually.

In real designs, coverage often samples on a clock edge.

Runnable Example — Clocked Covergroup

module clocked_coverage;

bit clk;

int addr;

always #5 clk = ~clk;

covergroup cg @(posedge clk);

coverpoint addr {

bins low = {[0:3]};

bins high = {[12:15]};

}

endgroup

cg cov = new();

initial begin

clk = 0;

repeat (10) begin

addr = $urandom_range(0,15);

#10;

end

endmodule

Why This Matters

Sampling is synchronized
Values are captured at meaningful moments

Less manual control, fewer mistakes

Common Practical Mistakes (Seen in Code)

Sampling before signals stabilize
Creating too many bins without intent
Crossing everything “just because”
Forgetting to exclude illegal scenarios

Coverage should reflect design questions, not curiosity.

A Simple Mental Checklist Alice Uses

Before writing coverage, Alice asks:

What scenarios matter?
Which combinations are critical?
What must never happen?
When should sampling occur?

If these are clear, coverage writes itself.

One Sentence to Remember

Cross coverage checks combinations, ignore bins remove noise, and illegal bins flag forbidden behavior.

Interview questions Coverage Fundamentals

Q1. What problem does coverage solve that assertions cannot?

Q2. Why is random testing without coverage considered unsafe?

Q3. Is 100% code coverage sufficient to sign off verification? Why or why not?

2. Functional Coverage Mechanics

Q4. What is a covergroup, and when is it sampled?

Q5. What is the role of bins in functional coverage?

Q6. What happens if you forget to sample a covergroup?

3. Cross Coverage (Where Interviews Go Deeper)

Q7. Why is cross coverage necessary even when individual coverpoints look covered?

Q8. Give one realistic situation where cross coverage is critical.

4. Ignore & Illegal Bins (Very High ROI)

Q9. When should you use ignore bins instead of constraints?

Q10. What is the difference between illegal bins and assertions?

5. Coverage + Randomization Thinking

Q11. How do constraints and coverage work together in a verification environment?

Q12. What does it indicate if coverage stops improving even after many random tests?

6. Sampling & Trustworthiness

Q13. Why is sampling time critical for coverage correctness?

Q14. Can coverage ever give a misleading sense of completeness? Explain how.