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Building a UVM Agent for AXI Interface: Step-by-Step Guide

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In the previous article, we discussed the AXI interface construct, which forms the backbone of communication between various components in a design. To briefly recap, the AXI interface (`axi_if`) was defined using SystemVerilog and facilitated the exchange of transactions such as read and write requests between the DUT (Design Under Test) and testbench components. With that foundation laid, we are ready to dig deeper into developing a UVM agent that interacts seamlessly with the AXI interface. In this article, we will take a step-by-step approach to build a UVM agent comprising the driver, monitor, sequencer, and configuration.

The UVM agent acts as a bundle containing critical components — the driver (`drv`), which executes transactions received from the sequencer (`seqr`); the monitor (`mon`), which observes data on the interface; and the configuration (`cfg`), specifying key settings such as AXI address and data widths. Together, these elements enable us to intelligently control and observe the AXI interface to ensure accurate transactions between the IP and testbench.

To understand this, imagine two friends exchanging items (representing data). One of the friends is responsible for writing notes to a board (driver), while the other quietly observes and verifies the notes (monitor). Both of them work based on instructions received from a coordinator (sequencer) who knows what needs to be written or verified. Before starting, they all agree on certain rules like the size of the board (configuration). This analogy forms a simple representation of how the UVM agent components interact.