📦SPI Data Frames and Packet Structure

Introduction

In SPI (Serial Peripheral Interface), data is not simply transmitted as continuous streams it is organized into structured frames or packets. These frames define how bits are grouped, interpreted, and synchronized between a master and one or more slave devices.

Unlike higher-level communication protocols, SPI does not enforce a strict universal packet format. Instead, manufacturers define frame structures based on device requirements. This flexibility is powerful, but it also means engineers must understand how different frame sizes and field organizations work in practice.

This chapter explores SPI data frames in depth, focusing on 8-bit, 16-bit, 24-bit, and 32-bit transfers, as well as command, address, data, and status fields commonly used in real devices.

1. Understanding SPI Data Frames

An SPI frame is a structured group of bits transmitted during a single chip-select (CS) active cycle. Each frame is synchronized by the clock (SCLK) and shifted bit-by-bit through MOSI and MISO lines.

A typical SPI transaction includes:

Command phase
Address phase
Data phase
Optional status/response phase

Not every device uses all phases, but these logical divisions are common in memory chips, sensors, and ADC/DAC devices.

The frame begins when CS is pulled LOW and ends when CS returns HIGH.

2. 8-bit SPI Transfers

The 8-bit transfer is the most fundamental SPI frame size and is widely used in microcontrollers and simple peripherals.

Structure:

8 bits per transaction
Usually represents:
- A command byte OR
- A single data byte

Example Use Cases:

Configuration registers
Simple sensor reads
Control signals

Characteristics:

Fast and efficient for small operations
Easy to implement in firmware
Often used in repeated bursts

Example Frame:

[ 8-bit Command ] [ 8-bit Data ]

In many systems, multiple 8-bit transfers are chained to build larger operations.

3. 16-bit SPI Transfers

16-bit SPI frames are common in devices that require more precision or combined instruction-data formatting.

Structure:

Single 16-bit shift operation
Can represent:
- 8-bit command + 8-bit data
- 16-bit data value

Example Use Cases:

Digital potentiometers
ADC readings
Display controllers

Advantages:

Reduces CS toggling overhead
Improves throughput compared to separate 8-bit cycles

Example Frame:

[ Command (8 bits) | Data (8 bits) ]

Or:

[ 16-bit Data Value ]

4. 24-bit SPI Transfers

24-bit frames are frequently used in mixed command-address systems, especially in memory and sensor devices.

Structure:

Typically divided into:
- 8-bit command
- 16-bit data OR address
Sometimes used as:
- 8-bit command + 16-bit payload

Example Use Cases:

Flash memory operations
Precision ADCs
Sensor registers with extended addressing

Example Frame:

[ Command (8) | Address (16) ]

This structure allows addressing up to 65,536 locations in a single operation, making it ideal for medium-complexity devices.

5. 32-bit SPI Transfers

32-bit frames are used in more advanced or high-precision systems where larger data words or combined multi-field operations are needed.

Structure Variations:

8-bit command + 24-bit address
16-bit command + 16-bit data
Full 32-bit data payload

Example Use Cases:

High-resolution sensors (24-bit ADC + overhead bits)
FPGA configuration registers
Complex memory-mapped devices

Example Frame:

[ Command (8) | Address (24) ]

Or:

[ Data (32-bit value) ]

Advantages:

Efficient for high-data operations
Minimizes transaction overhead
Suitable for high-speed SPI modes

6. Command Fields in SPI Frames

The command field defines the operation requested by the master device.

Common command types:

Read register
Write register
Start conversion
Reset device
Burst read/write

Characteristics:

Usually 8 bits long
Sent first in most SPI devices
Decoded by the slave to determine next steps

Example:

0x03 → Read command 0x0A → Write command

The command determines how subsequent bits are interpreted.

7. Address Fields

Address fields specify the target location inside a device.

Typical usage:

Memory registers
Sensor configuration maps
EEPROM/Flash locations

Common sizes:

8-bit (256 locations)
16-bit (65,536 locations)
24-bit (large memory spaces)

Example:

[ Command ] [ Address High Byte ] [ Address Low Byte ]

Addressing allows SPI devices to scale from simple registers to complex memory systems.

8. Data Fields

The data field contains the actual payload being written or read.

Characteristics:

Variable length depending on device
Can be 8, 16, 24, or 32 bits
May support burst mode transfers

Example:

Sensor output value
Configuration register data
Memory content

In read operations, the slave places data on MISO while the master provides dummy clocks.

9. Status Fields

Some SPI devices include a status response after command execution.

Purpose:

Indicate success or failure
Show busy/idle state
Provide error flags
Signal data readiness

Example status bits:

BUSY
ERROR
READY
WRITE ENABLE LATCH

Example:

[ Status Byte ] Bit 0 → Ready Bit 1 → Error Bit 2 → Busy

Status fields are especially common in flash memory and ADC devices.

10. Frame Organization in Real Devices

Real SPI devices combine multiple frame concepts into structured communication sequences.

Example: SPI Flash Memory Read

Command phase

0x03 (Read)

Address phase

24-bit address (A23–A0)

Data phase

Continuous streaming of bytes

Example: SPI Sensor Read

Master sends command
Slave returns status
Master clocks data out

[ Command ] → [ Status ] → [ Data ]

11. Continuous vs Discrete Frames

SPI can operate in two framing styles:

Discrete Frames:

CS toggles between each operation
Each frame is independent

Continuous Frames:

CS stays low
Multiple data blocks transmitted sequentially
Used for high-speed streaming

12. Practical Design Considerations

When designing SPI systems, engineers must consider:

Frame alignment with device datasheet
Correct bit order (MSB or LSB first)
CS timing requirements
Dummy cycles for read operations
Clock polarity and phase (CPOL/CPHA)

Incorrect framing is one of the most common causes of SPI communication failure.

🔑 Key Takeaways

SPI data frames form the structural foundation of SPI communication.
Although SPI is electrically simple, organizing data into 8-bit, 16-bit, 24-bit, and 32-bit frames enables communication with a wide range of devices.
Different frame sizes support applications ranging from basic sensor interfacing to complex memory and FPGA communication.
Understanding command, address, data, and status fields is essential for correctly interpreting device datasheets.
Proper frame organization helps engineers build reliable and efficient SPI systems.
Mastering SPI framing is a critical skill for embedded systems development.
SPI frame knowledge becomes especially important when working with mixed-signal devices, memory components, and high-speed peripherals.